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? semiconductor components industries, llc, 2012 may, 2012 ? rev. 4 1 publication order number: ncn8025/d ncn8025 / ncn8025a compact smart card interface ic the ncn8025 / ncn8025a is a compact and cost ? effective single smart card interface ic. it is dedicated for 1.8 v / 3.0 v / 5.0 v smart card reader/writer applications. the card v cc supply is provided by a built ? in very low drop out and low noise ldo. the device is fully compatible with the iso 7816 ? 3, emv 4.2, uicc and related standards including nds and other stb standards (nagravision, irdeto...). it satisfies the requirements specifying conditional access into set ? top ? boxes (stb) or conditional access modules (cam and cas). this smart card interface ic is available in a qfn ? 24 package (ncn8025a) providing all of the industry ? standard features usually required for stb smart card interface. it is also offered in a very compact package profile, qfn ? 16 (ncn8025), satisfying the requirements of cost ? efficiency and space ? saving requested by cam and sim applications. for details regarding device implementation refer to application note and8003/d, available upon request (please contact your local on semiconductor sales office or representative). features ? single ic card interface ? fully compatible with iso 7816 ? 3, emv4.2, uicc and related standards including nds and other stb standards (nagravision, irdeto...) ? 3 bidirectional buffered i/o level shifters (c4, c7 and c8) (qfn ? 24) ? 1 bidirectional i/o level shifter for the qfn ? 16 compact version ? 1.8 v, 3.0 v or 5.0 v 5 % regulated card power supply generation such as icc 70 ma ? regulator power supply: v ddp = 2.7 v to 5.5 v (@ 1.8 v), 3.0 v to 5.5 v (@ 3.0 v) & 4.85 v to 5.5 v (@ 5.0 v) ? independent power supply range on controller interface such as v dd = 2.7 v to 5.5 v ? handles class a, b and c smart cards ? short circuit protection on all card pins ? support up to 27 mhz input clock with internal division ratio 1/1, 1/2, 1/4 and 1/8 through clkdiv1 and clkdiv2 ? esd protection on card pins up to +8 kv (human body model) ? activation / deactivation sequences (iso7816 sequencer) ? fault protection mechanisms enabling automatic device deactivation in case of overload, overheating, card take ? off or power supply drop ? out (ocp, otp, uvp) ? interrupt signal int for card presence and faults ? external under ? voltage lockout threshold adjustment on vdd (poradj pin) (except qfn ? 16) ? available in 2 package formats: qfn ? 24 (ncn8025a) and qfn ? 16 (ncn8025) ? these are pb ? free devices typical application ? pay tv, set top box decoder with conditional access and pay ? per ? view ? conditional access module (cam / cas) ? sim card interface applications (uicc / usim) ? point of sales and transaction terminals ? electronic payment and identification see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information marking diagrams a = assembly location l = wafer lot y = year w = work week = pb ? free package http://onsemi.com ncn 8025a alyw qfn24 mn suffix case 485l 1 qfn16 mt suffix case 488ak ncn 8025 alyw (*note: microdot may be in either location)
ncn8025 / ncn8025a http://onsemi.com 2 cvcc caux1 cclk i/ouc crst pres vcc rst clk c4 gnd vpp i/o c8 det det gnd gnd 220 nf 1 2 3 4 5 6 7 8 smart card vdd vddp vdd vddp 100 nf clkdiv2 clkdiv1 vsel0 host controller data port gnd ncn8025a gnd caux2 gnd gnd ci/o 10 uf aux1uc aux2uc poradj rstin control 100 nf vdd r1 r2 clkin gnd vsel1 gnd 100 nf no figure 1. typical smart card interface application int cmdvcc pres 1 2 3 4 5 6 7 8 9 10 11 12 17 16 15 14 13 24 23 22 21 20 18 ncn8025a 25 exposed pad gnd caux2 ci/o pres vddp gnd vdd rstin clkin caux1 vsel0 1 2 3 4 16 15 14 13 exposed pad vddp 12 11 10 9 5678 clkin vdd rstin ci/o ncn8025 17 gnd vsel0 figure 2. ncn8025a ? qfn ? 24 pinout (top view) figure 3. ncn8025 ? qfn ? 16 pinout (top view) 19 gnd cclk crst cvcc poradj vsel1 clkdiv2 clkdiv1 aux2uc aux1uc i/ouc int cmdvcc pres pres int vsel1 clkdiv2 clkdiv1 i/ouc cclk crst cvcc cmdvcc
ncn8025 / ncn8025a http://onsemi.com 3 vsel1 vddp 17 11 cvcc 24 12 1.8 v / 3 v / 5 v ldo card pin level shifters & drivers vdd 18 clkin 19 25 gnd 14 rstin 5 cio 8 gnd 10 crst 9 cclk 16 gnd 4 pres 3 supply voltage monitoring thermal control card detection control logic and fault detection iso7816 sequencer 15 2 20 aux1uc 7 caux1 21 6 aux2uc caux2 1 vsel0 clock divider 23 22 clkdiv1 clkdiv2 13 poradj figure 4. ncn8025a block diagram (qfn ? 24 pin numbering) int cmdvcc pres i/ouc pin function and description pin (qfn24) pin (qfn16) name type description 1 1 vsel0 input allows selecting card v cc power supply voltage mode (5v/3v or 1.8v/3v ) vsel0 = low; cvcc = 5 v when vsel1 = high or 3 v when vsel1 = low vsel0 = high; cvcc = 1.8 v when vsel1 = high or 3 v when vsel1 = low 2 2 vddp power regulator power supply. 3 3 pres input card presence pin active (card present) when pres = low. a built ? in debounce timer of about 8 ms is activated when a card is inserted. convenient for normally open (no) smart card connector. 4 ? pres input card presence pin active (card present) when pres = high. a built ? in debounce timer of about 8 ms is activated when a card is inserted. convenient for normally closed (nc) smart card connector. 5 4 ci/o input/ output this pin handles the connection to the serial i/o (c7) of the card connector. a bi ? directional level translator adapts the serial i/o signal between the card and the micro controller. a 11 k (typical) pull up resistor to cvcc provides a high impedance state for the smart card i/o link.
ncn8025 / ncn8025a http://onsemi.com 4 pin function and description pin (qfn24) description type name pin (qfn16) 6 ? caux2 input/ output this pin handles the connection to the chip card?s serial auxiliary aux2 i/o pin (c8). a bi ? directional level translator adapts the serial i/o signal between the card and the micro controller. a 11 k (typical) pull up resistor to cvcc provides a high impedance state for the smart card c8 pin. 7 ? caux1 input/ output this pin handles the connection to the chip card?s serial auxiliary aux1 i/o pin (c4). a bi ? directional level translator adapts the serial i/o signal between the card and the micro controller. a 11 k (typical) pull up resistor to cvcc provides a high impedance state for the smart card c4 pin. 8 ? gnd ground card ground 9 5 cclk output this pin is connected to the clock card connector?s pin (chip card?s pin c3). the clock signal comes from the clkin input through clock dividers and level shifter. 10 6 crst output this pin is connected to the chip card?s reset pin (c2) through the card connector. a level translator adapts the external reset (rstin) signal to the smart card. 11 7 cvcc power output this pin is connected to the smart card power supply pin (c1). an internal low dropout regulator is programmable using the pins vsel0 and vsel1 to supply either 5 v or 3 v or 1.8 v output voltage. an external distributed ceramic capacitor ranging from 80 nf to 1.2 f recommended must be connected across cvcc and cgnd. this set of capacitor (if distributed) must be low esr (< 100 m ). 12 8 cmdvcc input command v cc pin. activation sequence enable/disable pin (active low). the activation sequence is enabled by toggling cmdvcc high to low and when a card is present. 13 ? poradj input power ? on reset threshold adjustment input pin for changing the reset threshold (v dd uvlo threshold) thanks to an external resistor power divider. needs to be connected to ground when unused. 14 9 rstin input this reset input connected to the host and referred to vdd (microcontroller side), is connected to the smart card reset pin through the internal level shifter which translates the level according to the cvcc programmed value. 15 10 vdd power input this pin is connected to the system controller power supply. it configures the level shifter input stage to accept the signals coming from the controller. a 0.1 f decoupling capacitor shall be used. when v dd is below 2.30 v typical the card pins are disabled. 16 ? gnd ground ground 17 11 int output the interrupt request is activated low on this pin. this is enabled when a card is present and the card presence is detected by pres or pres pins. similarly an interrupt is generated when cvcc is overloaded. inverter output (an open ? drain output configuration with 50 k pull ? up resistor is available under request (metal change)). 18 12 clkin input clock input for external clock 19 13 i/ouc input / output this pin is connected to an external micro ? controller. a bi ? directional level translator adapts the serial i/o signal between the smart card and the external controller. a built ? in constant 11 k (typical) resistor provides a high impedance state. 20 ? aux1uc input / output this pin is connected to an external micro ? controller. a bi ? directional level translator adapts the serial c4 signal between the smart card and the external controller. a built ? in constant 11 k (typical) resistor provides a high impedance state. 21 ? aux2uc input / output this pin is connected to an external micro ? controller. a bi ? directional level translator adapts the serial c8 signal between the smart card and the external controller. a built ? in constant 11 k (typical) resistor provides a high impedance state. 22 14 clkdiv1 input this pin coupled with clkdiv2 is used to program the clock frequency division ratio (table 2). 23 15 clkdiv2 input this pin coupled with clkdiv1 is used to program the clock frequency division ratio (table 2). 24 16 vsel1 input allows selecting card v cc power supply voltage. vsel0 = low: cvcc = 5 v when vsel1 = high or 3 v when vsel1 = low. vsel0 = high: cvcc = 1.8 v when vsel1 = high or 3 v when vsel1 = low. 25 17 gnd ground regulator power supply ground note: all information below refers to qfn ? 24 pin numbering unless otherwise noted. this information can be transposed to the qfn ? 16 package according to the above ?pin function and description? table.
ncn8025 / ncn8025a http://onsemi.com 5 attributes characteristics values esd protection human body model (hbm) (note 1) card pins (card interface pins 3 ? 11) all other pins machine model (mm) card pins (card interface pins 3 ? 11) all other pins 8 kv 2 kv 400 v 150 v moisture sensitivity (note 2) qfn ? 24 and qfn ? 16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in meets or exceeds jedec spec eia/jesd78 ic latch ? up test 1. human body model (hbm), r = 1500 , c = 100 pf. 2. for additional information, see application note and8003/d. maximum ratings (note 3) rating symbol value unit regulator power supply voltage v ddp ? 0.3 v ddp 5.5 v power supply from microcontroller side v dd ? 0.3 v dd 5.5 v external card power supply cvcc ? 0.3 cvcc 5.5 v digital input pins v in ? 0.3 v in v dd v digital output pins (i/ouc, aux1uc, aux2uc, int ) v out ? 0.3 v out v dd v smart card output pins v out ? 0.3 v out cvcc v thermal resistance junction ? to ? air (note 4) qfn ? 24 qfn ? 16 r ja 37 48 c/w operating ambient temperature range t a ? 40 to +85 c operating junction temperature range t j ? 40 to +125 c maximum junction temperature t jmax +125 c storage temperature range t stg ? 65 to + 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = +25 c. 4. exposed pad (gnd) must be connected to pcb.
ncn8025 / ncn8025a http://onsemi.com 6 power supply section (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) symbol rating min typ max unit v ddp regulator power supply, cvcc = 5.0 v, |icc| 70 ma (emv conditions) |icc| 70 ma (nds conditions) cvcc = 3.0 v, |icc| 70 ma cvcc = 1.8 v, |icc| 70 ma 4.75 4.85 3.0 2.7 5.0 5.0 5.5 5.5 5.5 5.5 v i ddp inactive mode (cmdvcc = high) ? ? 1 a i ddp dc operating supply current, f clkin = 10 mhz, cout cclk = 33 pf, |i cvcc | = 0 (cmdvcc = low) ? ? 3.0 ma i ddp dc operating supply current, cvcc = 5 v, i cvcc = 70 ma cvcc = 3 v, i cvcc = 70 ma cvcc = 1.8 v, i cvcc = 70 ma ? ? ? ? ? ? 150 150 150 ma v dd operating voltage 2.7 ? 5.5 v i vdd inactive mode ? standby current (cmdvcc = high) ? ? 60 a i vdd operating current ? f clk_in = 10 mhz , cout cclk = 33 pf |i cvcc | = 0 (cmdvcc = low) ? ? 1 ma uvlov dd under voltage lock ? out (uvlo), no external resistor at pin poradj (connected to gnd), falling v dd level 2.20 2.30 2.40 v uvlohys uvlo hysteresis, no external resistor at pin poradj (connected to gnd) 50 100 180 mv poradj pin v porth+ external rising threshold voltage on v dd for power on reset ? pin poradj 1.20 1.27 1.34 v v porth ? external falling threshold voltage on v dd for power on reset ? pin poradj 1.15 1.20 1.28 v v porhys hysteresis on v porth (pin poradj) 30 80 100 mv t por width of power ? on reset pulse (note 5) no external resistor on poradj external resistor on poradj 4 4 8 8 12 12 ms ms i il low level input leakage current, v il < 0.5 v (pull ? down source current) 5 a low dropout regulator c cvcc output capacitance on card power supply cvcc (note 6) 0.08 0.32 1.2 f cvcc output card supply voltage (including ripple) 1.8 v cvcc mode @ icc 70 ma 3.0 v cvcc mode @ icc 70 ma 5.0 v cvcc mode @ icc 70 ma with 4.85 v vddp 5.5 v (nds) 5.0 v cvcc mode @ icc 70 ma with 4.75 v vddp 5.5 v (emv) 1.70 2.85 4.75 4.60 1.80 3.00 5.00 5.00 1.90 3.15 5.25 5.25 v v v cvcc current pulses 15 nas (t < 400 ns & |i cc | < 100 ma peak) (note 5) 1.8 v mode / ripple 250 mv (2.7 v v ddp 5.5 v) current pulses 40 nas (t < 400 ns & |i cc | < 200 ma peak) 3.0 v mode / ripple 250 mv (2.9 v v ddp 5.5 v) current pulses 40 nas (t < 400 ns & |i cc | < 200 ma peak) 5.0 v mode / ripple 250 mv (4.85 v v ddp 5.5 v) 1.66 2.70 4.60 1.80 3.00 5.00 1.90 3.30 5.30 v v v i cvcc card supply current @ cvcc = 1.8 v @ cvcc = 3.0 v @ cvcc = 5.0 v 70 70 70 ma i cvcc_sc short ? circuit current ? cvcc shorted to ground 120 150 ma v cvcc output card supply voltage ripple peak ? to ? peak ? f ripple = 100 hz to 200 mhz (load transient frequency with 65 ma peak current and 50% duty cycle) (note 5) 300 mv cvcc sr slew rate on cvcc turn ? on / turn ? off (note 5) 0.22 v/ s 5. guaranteed by design and characterization. 6. these values take into account the tolerance of the cms capacitor used. cms capacitor very low esr (< 100 m , x5r / x7r).
ncn8025 / ncn8025a http://onsemi.com 7 host interface section clkin, rstin, i/ouc, aux1uc, aux2uc, clkdiv1, clkdiv2, cmdvcc , vsel0, vsel1 (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) symbol rating min typ max unit f clkin clock frequency on pin clkin (note 7) ? ? 27 mhz v il input voltage level low: clkin, rstin, clkdiv1, clkdiv2, cmdvcc , vsel0, vsel1 ? 0.3 ? 0.3 x v dd v v ih input voltage level high: clkin, rstin, clkdiv1, clkdiv2, cmdvcc , vsel0, vsel1 0.7 x v dd ? v dd + 0.3 v |i il | clkdiv1, clkdiv2, cmdvcc , rstin, clkin, vsel0, vsel1 low level input leakage current, v il = 0 v ? ? 1 a |i ih | clkdiv1, clkdiv2, cmdvcc , rstin, clkin, vsel0, vsel1 low level input leakage current, v ih = v dd ? ? 1 a v il input voltage level low: i/ouc, aux1uc, aux2uc ? 0.3 0.5 v v ih input voltage level high: i/ouc, aux1uc, aux2uc 0.7 x v dd v dd + 0.3 v |i il | i/ouc, aux1uc, aux2uc low level input leakage current, v il = 0 v ? ? 600 a |i ih | i/ouc, aux1uc, aux2uc high level input leakage current, v ih = v dd ? ? 10 a v oh v ol t ri/fi t ro/fo i/ouc, aux1uc, aux2uc data channels, @ cs 30 pf high level output voltage (crd_i/o = caux1 = caux2 = cvcc) i oh = ? 40 a for v dd > 2 v (i oh = ? 20 a for v dd 2 v) low level output voltage (crd_i/o = caux1 = caux2 = 0 v) i ol = + 1 ma input rising/falling times (note 7) output rising/falling times (note 7) 0.75 x v dd 0 ? ? ? ? ? ? v dd + 0.1 0.3 1.2 0.1 v v s s r pu i/0uc, aux1uc, aux2uc pull up resistor 8 11 16 k v oh output high voltage int @ i oh = ? 15 a (source) 0.75 x v dd ? ? v v ol output low voltage int @ i ol = 2 ma (sink) 0 ? 0.30 v r int int pull up resistor (open ? drain output configuration option) (note 8) 40 50 60 k 7. guaranteed by design and characterization. 8. option available under request (metal change). the current option is an inverter ? like output.
ncn8025 / ncn8025a http://onsemi.com 8 smart card interface section ci/o, caux1, caux2, cclk, crst, pres, pres (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) symbol rating min typ max unit v oh v ol t r t f t r/f td crst @ cvcc = 1.8 v, 3.0 v, 5.0 v output reset v oh @ i rst = ? 200 a output reset v ol @ i rst = 200 a output reset rise time @ c out = 100 pf (note 9) output reset fall time @ c out = 100 pf (note 9) output rise/fall times @ cvcc = 1.8 v & c out = 100 pf (note 9) rstin to crst delay ? reset enabled (note 9) 0.9 x cvcc 0 ? ? ? ? ? ? ? ? ? ? cvcc 0.20 100 100 200 2 v v ns ns ns s f crdclk v oh v ol f dc t rills t ulsa sr cclk @ cvcc = 1.8 v, 3.0 v or 5.0 v output frequency (note 9) output cclk v oh @ i clk = ? 200 a output cclk v ol @ i clk = 200 a output duty cycle (note 9) rise & fall time output cclk rise time @ c out = 33 pf (note 9) output cclk fall time @ c out = 33 pf (note 9) slew rate @ c out = 33 pf (cvcc = 3.0 v or 5.0 v) (note 9) ? 0.9 x cvcc 0 45 ? ? 0.2 ? ? ? ? ? ? ? 27 cvcc +0.2 55 16 16 ? mhz v v % ns ns v/ns v ih v il |i il | |i ih | v oh v ol t ri / fi t ro / fo caux1, caux2, ci/o @ cvcc = 1.8 v, 3.0 v, 5.0 v input voltage high level 1.8 v mode 3.0 v mode 5.0 v mode input voltage low level 1.8 v mode 3.0 v and 5.0 v modes low level input current v il = 0 v high level input current v ih = cvcc output v oh @ i oh = ? 40 a for cvcc = 3.0 v and 5.0 v @ i oh = ? 20 a for cvcc = 1.8 v output v ol @ i ol = 1 ma, v il = 0 v input rising/falling times (note 9) output rising/falling times / c out = 80 pf (note 9) 1.2 1.6 2.3 ? 0.30 ? 0.30 ? ? 0.75 x cvcc 0.75 x cvcc 0 ? ? ? ? ? ? ? ? ? ? ? ? cvcc + 0.3 cvcc + 0.3 cvcc + 0.3 0.50 0.80 600 10 cvcc + 0.1 cvcc + 0.1 0.30 1.2 0.1 v v v v v a a v v v s s f bidi maximum data rate through bidirectional i/o, aux1 & aux2 channels (note 9) ? ? 1 mhz r pu caux1, caux2, ci/o pull ? up resistor 8 11 16 k t io propagation delay iouc ? > ci/o and ci/o ? > iouc (falling edge) (note 9) ? ? 200 ns tpu active pull ? up pulse width buffers i/o, aux1 and aux2 (note 9) ? ? 200 ns c in input capacitance on data channels ? ? 10 pf v ih v il pres, pres card presence voltage high level card presence voltage low level 0.7 x v dd ? 0.3 ? ? v dd + 0.3 0.3 x v dd v |i ih | |i il | pres, pres high level input leakage current, v ih = v dd pres pres low level input leakage current, v il = 0 v pres pres 5 5 10 1 1 10 a
ncn8025 / ncn8025a http://onsemi.com 9 smart card interface section ci/o, caux1, caux2, cclk, crst, pres, pres (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) symbol unit max typ min rating t debounce debounce time pres and pres (note 9) 5 8 12 ms i ci/o ci/o, caux1, caux2 current limitation ? ? 15 ma i cclk cclk current limitation ? ? 70 ma i crst crst current limitation ? ? 20 ma t act activation time (note 9) 30 ? 100 s t deact deactivation time (note 9) 30 ? 250 s temp sd shutdown temperature (note 9) ? 150 ? c 9. guaranteed by design and characterization. power supply the ncn8025 / ncn8025a smart card interface has two power supplies: v dd and v ddp . v dd is common to the system controller and the interface. the applied v dd range can go from 2.7 v up to 5.5 v. if v dd goes below 2.30 v typical (uvlo vdd ) a power ? down sequence is automatically performed. in that case the interrupt (int ) pin is set low. a low drop ? out (ldo) and low noise regulator is used to provide the 1.8 v, 3 v or 5 v power supply voltage (cvcc) to the card. v ddp is the ldo?s input voltage. cvcc is the ldo output. the typical distributed reservoir output capacitor connected to cvcc is 100 nf + 220 nf. the capacitor of 100 nf is connected as close as possible to the cvcc?s pin and the 220 nf one as close as possible to the card connector c1 pin. both feature very low esr values (lower than 50 m ). the decoupling capacitors on v dd and v ddp respectively 100 nf and 10 f + 100 nf have also to be connected close to the respective ic pins. the cvcc pin can source up to 70 ma at 1.8 v, 3 v and 5 v continuously over the v ddp range (see corresponding specification table), the absolute maximum current being internally limited below 150 ma (typical at 120 ma). the card v cc voltage (cvcc) can be programmed with the pins vsel0 and vsel1 and according to the below table: table 1. cvcc programming vsel0 vsel1 cvcc 0 0 3.0 v 0 1 5.0 v 1 0 3.0 v 1 1 1.8 v vsel0 can be used to select the cvcc programming mode which can be 5v/3v (vsel0 connected to ground) or 1.8v/3v (vsel0 connected to v dd ). vsel0 and vsel1 are usually programmed before activating the smart card interface that is when /cmdvcc is high. there?s no specific sequence for applying v dd or v ddp . they can be applied to the interface in any sequence. after powering the device int pin remains low until a card is inserted. supply voltage monitoring the supply voltage monitoring block includes the power ? on reset (por) circuitry and the under ? voltage lockout (uvlo) detection (v dd voltage dropout detection). poradj pin allows the user, according to the considered application, to adjust the v dd uvlo threshold. if not used poradj pin is connected to ground (recommended even if it may be left unconnected). the input supply voltage is continuously monitored to prevent under voltage operation. at power up, the system initializes the internal logic during por timing and no further signal can be provided or supported during this period. the system is ready to operate when the input voltage has reached the minimum v dd . considering this, the ncn8025 / ncn8025a will detect an under ? voltage situation when the input supply voltage will drop below 2.30 v typical. when v dd goes down below the uvlo falling threshold a deactivation sequence is performed. the device is inactive during power ? on and power ? off of the v dd supply (8 ms reset pulse). poradj pin is used to modify the uvlo threshold according to the below relationship considering an external resistor divider r1 / r2 (see block diagram figure 1): uvlo r1 r2 r2 v por (eq. 1) if poradj is connected to ground the v dd uvlo threshold (v dd falling) is typically 2.30 v. in some cases it can be interesting to adjust this threshold at a higher value and by the way increase the v dd supply dropout detection level which enables a deactivation sequence if the v dd voltage is too low. for example, there are microcontrollers for which the minimum supply voltage insuring a correct operating is higher than 2.6 v; increasing uvlo vdd (v dd falling) is consequently necessary. considering for instance a resistor bridge with r1 = 56 k , r2 = 42 k and v por ? = 1.27 v typical the v dd dropout detection level can be increased up to: uvlo 56k 42k 42k v por ? 2.96 v (eq. 2)
ncn8025 / ncn8025a http://onsemi.com 10 clock divider: the input clock can be divided by 1/1, 1/2, 1/4, or 1/8, depending upon the specific application, prior to be applied to the smart card driver. these division ratios are programmed using pins clkdiv1 and clkdiv2 (see table 2). the input clock is provided externally to pin clkin. table 2. clock frequency programming clkdiv1 clkdiv2 f cclk 0 0 clkin / 8 0 1 cklkin / 4 1 0 clkin 1 1 clkin / 2 the clock input stage (clkin) can handle a 27 mhz maximum frequency signal. of course, the ratio must be defined by the user to cope with smart card considered in a given application in order to avoid any duty cycle out of the 45% / 55% range specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio 1/2, 1/4 or 1/8. on the other hand, the output signal duty cycle cannot be guaranteed 50% if the division ratio is 1 and if the input duty cycle signal is not within the 46% ? 56% range at the clkin input. when the signal applied to clkin is coming from the external controller, the clock will be applied to the card under the control of the microcontroller or similar device after the activation sequence has been completed. data i/o, aux1 and aux2 level shifters the three bidirectional level shifters i/o, aux1 and aux2 adapt the voltage difference that might exist between the micro ? controller and the smart card. these three channels are identical. the first side of the bidirectional level shifter dropping low (falling edge) becomes the driver side until the level shifter enters again in the idle state pulling high ci/o and i/ouc. passive 11 k pull ? up resistors have been internally integrated on each terminal of the bidirectional channel. in addition with these pull ? up resistors, an active pull ? up circuit provides a fast charge of the stray capacitance. the current to and from the card i/o lines is limited internally to 15 ma and the maximum guaranteed frequency on these lines is 1 mhz. standby mode after a power ? on reset, the circuit enters the standby mode. a minimum number of circuits are active while waiting for the microcontroller to start a session: ? all card contacts are inactive ? pins i/ouc, aux1uc and aux2uc are in the high ? impedance state (11 k pull ? up resistor to v dd ) ? card pins are inactive and pulled low ? supply voltage monitoring is active power ? up in the standby mode the microcontroller can check the presence of a card using the signals int and cmdvcc as shown in table 3: table 3. card presence state int cmdvcc state high high card present low high card not present if a card is detected present (pres or pres active) the controller can start a card session by pulling cmdvcc low. card activation is run (t0, figure 6). this power ? up sequence makes sure all the card related signals are low during the cvcc positive going slope. these lines are validated when cvcc is stable and above the minimum voltage specified. when the cvcc voltage reaches the programmed value (1.8 v, 3.0 v or 5.0 v), the circuit activates the card signals according to the following sequence (figure 6): ? cvcc is powered ? up at its nominal value (t1) ? i/o, aux1 and aux2 lines are activated (t2) ? then clock is activated and the clock signal is applied to the card (typically 500 ns after i/os lines) (t3) ? finally the reset level shifter is enabled (typically 500 ns after clock channel) (t4) the clock can also be applied to the card using a rstin mode allowing controlling the clock starting by setting rstin low (figure 5). before running the activation sequence, that is before setting low cmdvcc rstin is set high. the following sequence is applied: ? the smart card interface is enable by setting cmdvcc low (rstin is high). ? between t2 (figure 5) and t5 = 200 s, rstin is reset to low and cclk will start precisely at this moment allowing a precise count of clock cycles before toggling crst low to high for atr (answer to reset) request. ? crst remains low until 200 s; after t5 = 200 s crst is enabled and is the copy of rstin which has no more control on the clock. if controlling the clock with rstin is not necessary ( normal mode ), then cmdvcc can be set low with rstin low. in that case, clk will start minimum 500 ns after the transition on i/o (figure 6), and to obtain an atr, crst can be set high by rstin also about 500 ns after the clock channel activation (t act ). the internal activation sequence activates the different channels according to a specific hardware built ? in sequencing internally defined but at the end the actual activation sequencing is the responsibility of the application software and can be redefined by the micro ? controller to comply with the different standards and the different ways the standards manage this activation (for example light differences exist between the emv and the iso7816 standards).
ncn8025 / ncn8025a http://onsemi.com 11 crst cvcc cio cclk atr rstin figure 5. activation sequence ? rstin mode (rstin starting high) cmdvcc t0 t1 t2 t4 t5 ~200 s crst cvcc cio cclk atr rstin figure 6. activation sequence ? normal mode cmdvcc t0 t1 t2 t4 t3 t act
ncn8025 / ncn8025a http://onsemi.com 12 power ? down when the communication session is completed the ncn8025 / ncn8025a runs a deactivation sequence by setting high cmdvcc . the below power down sequence is executed: ? crst is forced to low ? cclk is set low 12 s after crst. ? ci/o, caux1 and caux2 are pulled low ? finally cvcc supply can be shut ? off. crst cvcc cio cclk figure 7. deactivation sequence cmdvcc t deact fault detection in order to protect both the interface and the external smart card, the ncn8025 / ncn8025a provides security features to prevent failures or damages as depicted here after. ? card extraction detection ? v dd under voltage detection ? short ? circuit or overload on cvcc ? dc/dc operation: the internal circuit continuously senses the cvcc voltage (in the case of either over or under voltage situation). ? dc/dc operation: under ? voltage detection on v ddp ? overheating ? card pin current limitation: in the case of a short circuit to ground. no feedback is provided to the external mpu. pres cvcc /int debounce debounce powerdown resulting of card extraction powerdown caused by short ? circuit figure 8. fault detection and interrupt management cmdvcc interrupt pin management: a card session is opened by toggling cmdvcc high to low. before a card session, cmdvcc is supposed to be in a high position. int is low if no card is present in the card connector (normally open or normally closed type). int is high if a card is present. if a card is inserted (int = high) and if v dd drops below the uvlo threshold then int pin drops low immediately. it switches high when v dd increases again over the uvlo limit (including hysteresis), a card being still present. during a card session, cmdvcc is low and int pin goes low when a fault is detected. in that case a deactivation is immediately and automatically performed (see figure 7). when the microcontroller resets cmdvcc to high it can sense the int level again after having got completed the deactivation.
ncn8025 / ncn8025a http://onsemi.com 13 as illustrated by figure 8 the device has a debounce timer of 8 ms typical duration. when a card is inserted, output int goes high only at the end of the debounce time. when the card is removed a deactivation sequence is automatically and immediately performed and int goes low. esd protection the ncn8025 / ncn8025a includes devices to protect the pins against the esd spike voltages. to cope with the different esd voltages developed across these pins, the built in structures have been designed to handle either 2 kv, when related to the micro controller side, or 8 kv when connected with the external contacts (hbm model). practically, the crst, cclk, ci/o, caux1, caux2, pres and pres pins can sustain 8 kv. the cvcc pin has the same esd protection and can source up to 70 ma continuously, the absolute maximum current being internally limited with a max at 150 ma. the cvcc current limit depends on v ddp and cvcc. application schematic 3.3 v microcontroller vcc rst clk c4 gnd vpp i/o c8 1 2 3 4 5 6 7 8 smart card r1 r2 vdd +3.3 v det normally open vdd +3.3 v vddp +5 v + 100 nf xtal1 xtal2 100 nf caux2 ci/o pres vddp vdd rstin clkin vsel0 1 2 3 4 5 6 789101112 17 16 15 14 13 24 23 22 21 20 19 18 exposed pad 25 gnd 220 nf 100 nf gnd 100 nf figure 9. application schematic vsel1 clkdiv2 clkdiv1 aux2uc aux1uc i/ouc caux1 gnd cclk crst cvcc poradj optional r1/r2 resistor divider ? if not used it is recommended to connect poradj to ground 10 f int pres cmdvcc ordering information device package shipping ? ncn8025amntxg qfn24 (pb ? free) 3000 / tape & reel NCN8025MTTBG qfn16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncn8025 / ncn8025a http://onsemi.com 14 package dimensions qfn24, 4x4, 0.5p case 485l ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d b 0.15 c a2 a a3 a e pin 1 identification 2x 0.15 c 2x 0.08 c 0.10 c a1 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.20 0.30 d 4.00 bsc d2 2.70 2.90 e 4.00 bsc e2 2.70 2.90 e 0.50 bsc l 0.30 0.50 24x l d2 b 1 6 7 18 13 19 e 12 e2 e 24 0.10 b 0.05 a c c ref
ncn8025 / ncn8025a http://onsemi.com 15 package dimensions qfn16, 3x3, 0.5 p case 488ak issue o 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm spacing between lead tip and flag. ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x 16x note 5 0.10 c 0.05 c a b note 3 k 16x exposed pad dim min max millimeters a 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k 0.20 ??? l 0.30 0.50 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncn8025/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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